On July 30, 2026, Union Semiconductor (USC) held a signing ceremony for its HITS advanced packaging R&D and industrialization project in Shanghai's Jiading District. With total investment expected to reach at least 7.5 billion yuan, the project targets five core technical bottlenecks including ultra-narrow pitch bump bonding and high-density interposer integration, aiming to build the packaging and interconnect foundation for AI servers and high-performance computing chips.
Project Overview: 7.5 Billion Yuan Bet on Advanced Packaging
According to "Invest Jiading," Union Semiconductor (Hefei) Co., Ltd. (USC) held a signing ceremony on July 30, 2026, in Nanxiang Town, Jiading District, Shanghai for its HITS advanced packaging R&D and industrialization project. The total investment is expected to reach at least 7.5 billion yuan, to build and operate an HITS advanced packaging process platform alongside an R&D headquarters.
USC Chairman Zheng Ruijun stated that the team is already in place. The next phase involves recruiting more talent to ensure solid progress in R&D and mass production, delivering self-controlled, high-quality products as quickly as possible. Once operational, the project will significantly boost Jiading's capacity for high-end advanced packaging and testing, strengthen collaborative innovation across the regional integrated circuit supply chain, and help attract top-tier talent.
Tackling Five Core Technical Bottlenecks
The HITS project focuses on five core technical bottlenecks in the advanced packaging field, each targeting critical "chokepoint" links in domestic high-end chips:
- Ultra-Narrow Pitch Bump Bonding: Solving precision connection challenges for high-density interconnection between chips and substrates
- High-Speed Chip-to-Memory Interconnects: Breaking through data transfer bottlenecks between AI computing chips and HBM high-bandwidth memory
- High-Density Interposer Integration: Enabling efficient signal routing between multiple chips in 2.5D/3D packaging
- Large-Size Multi-Chip Packaging: Supporting larger-scale heterogeneous integration to meet AI servers' extreme demand for computing density
- Efficient Thermal Management: Solving heat dissipation challenges for high-power chips to ensure system stability
| Technical Direction | Problem Solved | Target Application |
|---|---|---|
| Ultra-Narrow Pitch Bump Bonding | High-density interconnection precision | GPU/AI accelerator chip packaging |
| High-Speed Chip-to-Memory | Data transfer bandwidth bottleneck | AI servers, HPC |
| High-Density Interposer | Multi-chip signal routing | 2.5D/3D Chiplet packaging |
| Large-Size Multi-Chip | Computing density improvement | Data center AI training chips |
| Efficient Thermal Management | High-power heat dissipation | High-computing platforms |
Industry Context: China Advanced Packaging Enters New Investment Wave
USC's Jiading project is not an isolated event. Statistics show that between May and July 2026 alone, nearly 10 major advanced packaging projects were publicly disclosed nationwide, with total investment approaching 40 billion yuan, covering 2.5D/3D packaging, Chiplet integration, Fan-Out, high-density RDL, advanced flip-chip, and automotive-grade chip packaging.
Landmark projects during this period include:
- JCET: Announced on June 24 a 7.8 billion yuan advanced packaging and testing base in Shanghai Lingang, focusing on high-density RDL, ultra-fine-pitch bumping, large-scale heterogeneous integration, and Chiplet multi-chip packaging
- Forehope Electronic: Announced on June 26 a 10.3 billion yuan high-end semiconductor packaging and testing base in Yuyao, Zhejiang, covering bumping, 2.5D integration, flip-chip, and advanced wire-bonding
- Union Semiconductor (USC): Jiading project signed on July 30, with investment of at least 7.5 billion yuan
This investment wave differs fundamentally from previous cycles: rather than simple capacity expansion, it targets the most technically demanding segments of the packaging value chain, directly driven by AI and HPC chip demand.
Why Jiading? — The Northern Core of Shanghai's "One Body, Two Wings" IC Layout
As the northern core of Shanghai's "one body, two wings" integrated circuit layout, Jiading's industrial clustering effect continues to grow. Key data points:
- Jiading's IC industry scale is projected to reach 105.8 billion yuan in 2025
- Output from designated-sized enterprises is nearing 80 billion yuan
- The district has gathered over 700 IC-related firms, including 122 designated-sized enterprises
- Multiple key innovation centers, professional platforms, and core production lines have been established
The USC project's landing will fill Jiading's gap in high-end advanced packaging and testing, driving the regional packaging and testing sector toward high-end customization and high-value foundry services, further reducing dependence on foreign advanced packaging and testing capabilities for domestic high-end chips.
Global Perspective: Why Advanced Packaging Has Become Semiconductor's "Must-Win Battleground"
As Moore's Law slows, chip performance improvements increasingly rely on advanced packaging technology rather than pure process node shrinkage. TSMC's CoWoS, Intel's Foveros, and Samsung's X-Cube have become core competitive barriers for AI chip giants. USC's HITS project represents an important step in China's semiconductor industry accelerating its catch-up in advanced packaging, the critical track of the "post-Moore era."
For automotive and technology industry practitioners in Central Asia, Russia, and other emerging markets, China's advancing advanced packaging capabilities mean further strengthening of supply chain self-control for domestic automotive chips and AI chips. USC has accumulated rich experience in automotive-grade chips, and its extending technical capabilities toward industrial AIoT and embodied intelligence will provide more diversified chip supply options for the global smart vehicle and robotics industries. For more information, visit EX1000.COM.
